The present invention relates to a racing circuit which may select one of a number of request signals generated asynchronously by a plurality of processor units for requesting the exclusive use of a resource owned in common by them, thereby permitting the exclusive use of the common resource by one processor unit.
In the prior art racing circuits, these request signals are acknowledged and executed in the order of their occurrence, but the amount of required hardware is increased in proportion to .sub.n C.sub.2,* where n is the number of processor units, so that very complex circuitry results. There has been also invented and demonstrated a racing circuit of the type wherein a plurality of circuits having the same function and each assigned to a plurality of processor units, are arrayed in the form of a ring and a pulse or a train of pulses is circulated through these circuits in a predetermined order. Therefore, when the pulse or the train of pulses reaches one of these circuits which is connected to a processor unit which has been permitted to access and use a common resource, another processor unit is then permitted to access and use the common resource. This racing circuit, however, has a disadvantage in that the sequence of the occurrence of request signals is not taken into consideration. FNT *Number of combinations of n things taken 2 at a time.
In order to overcome these and other problems, there has been devised and demonstrated a racing circuit (U.S. Pat. No. 3,603,935) wherein in response to the timing signals from timing means which is synchronized with the timing signals for accessing a common resource common to a plurality of processor units, a plurality of request signals which are output from the processor units asynchronously are temporarily stored in memory means, one of the stored request signals is selected in accordance with the predetermined priority order so that the corresponding processor unit may access to the common resource during one memory cycle, the request from this processor unit may be disabled at the end of this memory cycle, and a next request signal is selected so that the above steps are cycled.
In this racing circuit, the acknowledgement and interruption of a request signal are made in synchronism with the timing signals. Especially the interruption of the request signal is made in response to a signal transmitted from a memory bank. Therefore the correct operations are ensured, but the interruption of the request signal is made at each memory cycle so that the processor unit cannot exclusively access and use the common resource for more than one memory cycle. Furthermore the request signal is interrupted in response to the address release signal transmitted within one memory cycle so that the processor unit cannot control a time during which it may access and use the common resource. The outputs from a priority selection circuit are stored in a memory means and then are output as an enable or permission signal for enabling the processor unit to access and use the common resource. The selected request signal disables a demand from a demand memory. As a result, a time allotted to the processor unit is controlled only by the common resource.